Circuits for controlling voltage and current using high-side and low-side field effect transistors (FETs) have many applications involving regulation of electrical power supplies. In such applications, current is supplied to a load through a junction between the source of a high-side FET and the drain of a low-side FET. A capacitor is often coupled in parallel with the load and an inductor is coupled in series with the capacitor and load. During part of a cycle of operation the high-side FET is turned on and the low-side FET is turned off allowing current to flow through the high-side FET to the inductor, capacitor and load. The current to the load increases as the capacitor charges. When the voltage across the load reaches some target level, the high-side FET is switched off and the low-side FET is switched on. The current through the load decreases as the capacitor discharges. The circuit is normally set up to trigger the switching of the gates to high-side on and low-side off if the current through the inductor changes from increasing to decreasing but the output voltage has not. This can lead to output voltage instability if the capacitor has a low equivalent series resistance (ESR).
FIG. 1 is a circuit diagram of a voltage/current controller circuit 100 of the prior art. The switching controller 100 includes a controller integrated circuit (IC) 101 a high-side FET 102 and a low-side FET 104. A drain DHS of the high-side FET 102 is electrically coupled to an input voltage VIN, a source SHS of the high-side FET 102 is electrically coupled to the drain DLS of the low-side FET 104. A source SLS of the low-side FET is electrically coupled to ground. Gates GHS and GLS of the high-side FET and low-side standard FET are electrically coupled to high-side output HS and a low-side output LS of the controller IC 101. When a sufficient voltage is applied to a gate of one of the FETS, current may flow between the corresponding source and drain. During voltage and/or current control operation an “on” voltage is typically applied to the high-side gate GHS when an “off” voltage is applied to the low-side gate GLS and vice versa. The controller IC 101 may receive an input signal at an input pin IN that drives the voltages supplied by the high-side and low-side outputs. An inductor 106 is coupled at a junction between a source SHS of the high-side FET 102 and a drain DLS of the low-side FET 104. A load 108 is coupled between the inductor 106 and ground. The voltage across the load 108 is referred to herein as the output voltage VO.
The circuit 100 may operate in a mode referred to as constant on time. In this mode, the gates GHS, GLS are held on or off for fixed periods of time after switching from “on” to “off” or vice versa. The output voltage is sampled e.g., using a voltage divider network 112 to provide a feedback voltage VFB and fed to a comparator 114 which compares the output voltage to a desired Target voltage Vtar from a target voltage generator 116. When the feedback voltage VFB is equal to a target voltage Vtar, the comparator triggers the controller IC to switch the gates from high-side on/low-side off to low-side on, high-side off or vice versa. In many current/voltage regulation applications it is common to couple a capacitor 110 to ground in parallel with the load 108. The capacitor delays the output voltage across the load 108 relative to the output current through the load 108. This can lead to an unstable output voltage VO in constant on-time operation as discussed below.
The above-described operation of the circuit 100 essentially relies on a ripple in the output voltage VO in order to regulate the output current. Unfortunately, output voltage ripple is often undesirable in certain applications of such circuits. It would be desirable to control the ESR so that the output voltage turns (changes from falling to rising) during the on-time. This sort of operation may be achieved if the ESR is sufficiently large that the behavior of the capacitor 110 is more “resistor-like” , i.e., the phase of the output voltage VO tends to be close to the phase of the current IL through the inductor 106. An example of such operation is illustrated in FIG. 2A. Each cycle starts by switching the high-side gate “on” and the low-side gate “off”. In “constant on-time” operation, this condition remains for a fixed period of time TON after which the high-side gate is switched off and the low-side gate is switched on. This condition remains until the output voltage falls below the target voltage Vtar. Note also that the gate voltages VHSG and VLSG switch from high to low once per cycle. If the ESR of the capacitor 110 is too small, however, the circuit behavior of the capacitor 110 is more “capacitor-like” meaning that the phase of the output voltage VO tends to lag behind the phase of the inductor current IL as shown in FIG. 2B. The output voltage may become unstable if the feedback voltage VFB lags so far behind the current that the comparator 114 is not able to trigger a new cycle until after the constant “on” time has expired. As noted above, the circuit 100 is normally set up to trigger the switching of the gates to high-side on and low-side off if the inductor current IL changes from increasing to decreasing but the output voltage VO has not. As a result, the gate voltages VHSG and VLSG may switch more than once per cycle and the output becomes unstable.
To overcome this, it is desirable to select the capacitor 110 such that it has an equivalent series resistance (ESR) that is large enough that the output voltage VO is more in phase with the current IL from the inductor 106 and the operation is stable as in FIG. 2A. For example, a ceramic capacitor with a 20 milliohm ESR may be replaced with a tantalum capacitor having an ESR of about 200-600 milliohms. However, this may be difficult to engineer since the controller IC 101 and FETS 102, 104 are often packaged by a first manufacturer and the load 108 and capacitor 110 are designed and implemented by a second manufacturer. Thus, the ESR is often out of control of the first manufacturer. Furthermore, the ESR of the capacitor 110 often depends on factors such as the manufacturing method, material and temperature of the capacitor, that are out of the control of both manufacturers.
One prior art solution is to emulate the on-time current through the inductor 110 with a current emulator and use the emulated current to control triggering of the FETs 102, 104. In this manner, the output voltage may be kept in phase with the emulated current. Unfortunately, the current emulator tends to be complicated to implement and may require additional hardware for which space may be limited. In addition, the inductance of the inductor 106 must be in a specific range for the current emulator to operate. Since other factors may determine the choice of inductor, this solution is not always a viable one. It is within this context that embodiments of the present invention arise.